URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] - Rev 173

Rev	Log message	Author	Age	Path
153	SdVerification: further development, not done by far	rkastl	4912d 15h	/sdhc-sc-core/trunk/
152	SdClockMaster: Generate InStrobe so that it the sd bus gets captured on the rising edge of the clock in high speed mode	rkastl	4912d 15h	/sdhc-sc-core/trunk/
151	Verification: + redesign: not functional yet	rkastl	4912d 15h	/sdhc-sc-core/trunk/
150	Testbed: + Simulation made possible + Write works - Sometimes the alignment in the block is not right	rkastl	4912d 15h	/sdhc-sc-core/trunk/
149	SdBFM: + mailbox mode	rkastl	4912d 15h	/sdhc-sc-core/trunk/
148	SdVerification: + CardModel: Execution thread which starts initialization and then receives token and parses them. TbdSd: + Added SdWbSdSynchronization.	rkastl	4912d 15h	/sdhc-sc-core/trunk/
147	Sd-Core: + Added checking of Busy signal after write	rkastl	4912d 15h	/sdhc-sc-core/trunk/
146	SdClockMaster: + fixed output of data at negedge of sclk in high speed mode	rkastl	4912d 15h	/sdhc-sc-core/trunk/
145	Verification: + SdCardModel and SdBFM seperated	rkastl	4912d 15h	/sdhc-sc-core/trunk/
144	Simulation files for tbTbdSd created. tbTbdSd is not done and TestWbMaster seems to be lost.	rkastl	4912d 15h	/sdhc-sc-core/trunk/