URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] - Rev 181

Rev	Log message	Author	Age	Path
161	Verification: CardModel: Check CRC on received data	rkastl	4912d 17h	/sdhc-sc-core/trunk/
160	Verification: Full random read and write single blocks sequence works with checks. Checking the CRC in the card model is missing. Writing at addresses above the card size is missing. Erasing is missing.	rkastl	4912d 17h	/sdhc-sc-core/trunk/
159	Verification: Further work: Checking RAM Actions and reading data is still missing	rkastl	4912d 17h	/sdhc-sc-core/trunk/
158	Verification: Work on Checking Functional coverage	rkastl	4912d 17h	/sdhc-sc-core/trunk/
157	Verification: Testcase with Reads works but Verification not completly implemented.	rkastl	4912d 17h	/sdhc-sc-core/trunk/
156	SdVerification: + Split a SdCoreTransaction into multiple WbTransactions: Proof of Concept with a ReadSingleBlock-Transaction + Finish after certain amount of time and present simulation result	rkastl	4912d 17h	/sdhc-sc-core/trunk/
155	SdVerification: continue to work on it, not done.	rkastl	4912d 17h	/sdhc-sc-core/trunk/
154	SdVerification: - started sending with mailboxes	rkastl	4912d 17h	/sdhc-sc-core/trunk/
153	SdVerification: further development, not done by far	rkastl	4912d 17h	/sdhc-sc-core/trunk/
152	SdClockMaster: Generate InStrobe so that it the sd bus gets captured on the rising edge of the clock in high speed mode	rkastl	4912d 17h	/sdhc-sc-core/trunk/