URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] - Rev 41

Rev	Log message	Author	Age	Path
21	Wishbone: Control signals into records, unfortunately signals with a width dependend on generics can not be used in records before VHDL2008.	rkastl	4924d 23h	/sdhc-sc-core/trunk/
20	Wishbone: Directions added to port, support for synchronous cycle termination added to entity (and therefore new types in the package were created)	rkastl	4925d 00h	/sdhc-sc-core/trunk/
19	Wishbone: Fixed syntax errors in WbSlave-Rtl-ea.vhdl Only commit after a sucessful compiler run.	rkastl	4925d 00h	/sdhc-sc-core/trunk/
18	Wishbone: Slave entity started, Build file generated	rkastl	4925d 00h	/sdhc-sc-core/trunk/
17	Fixed error introduced in last commit.	rkastl	4925d 00h	/sdhc-sc-core/trunk/
16	Indenting changed (vim) added an error to test the ci-system	rkastl	4925d 00h	/sdhc-sc-core/trunk/
15	Support quartus tcl scripts in the Makefiles	rkastl	4925d 00h	/sdhc-sc-core/trunk/
14	Moved the Makefiles to root.	rkastl	4925d 00h	/sdhc-sc-core/trunk/
13	Made simulation makefiles recursive so all simulations can be started from a common point.	rkastl	4925d 00h	/sdhc-sc-core/trunk/
12	Headless quartus compile script.	rkastl	4925d 00h	/sdhc-sc-core/trunk/