URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] - Rev 155

Rev	Log message	Author	Age	Path
132	SdData: Refactoring, not done. Testbench works again, but does not really test anything.	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/
130	SdClockMaster: Formal verification	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/
129	SdClockMaster: Redesigned, not finished. Tb with PSL assertions.	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/
128	Sim: Support for psl files added.	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/
125	Write works in simulation	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/
124	Write: SdClk is disabled, if no data is available.	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/
122	SdController: Initial read support	rkastl	4924d 22h	/sdhc-sc-core/trunk/src/
121	SdWbSlave inserted into SdTop. SdController does not use it yet.	rkastl	4924d 22h	/sdhc-sc-core/trunk/src/