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[/] [sdhc-sc-core/] [trunk/] [src/] - Rev 156

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Rev Log message Author Age Path
133 SdData: Further refactoring rkastl 4928d 13h /sdhc-sc-core/trunk/src/
132 SdData: Refactoring, not done.
Testbench works again, but does not really test anything.		 rkastl 4928d 13h /sdhc-sc-core/trunk/src/
130 SdClockMaster: Formal verification rkastl 4928d 13h /sdhc-sc-core/trunk/src/
129 SdClockMaster: Redesigned, not finished. Tb with PSL assertions. rkastl 4928d 13h /sdhc-sc-core/trunk/src/
128 Sim: Support for psl files added. rkastl 4928d 13h /sdhc-sc-core/trunk/src/
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4928d 13h /sdhc-sc-core/trunk/src/
125 Write works in simulation rkastl 4928d 13h /sdhc-sc-core/trunk/src/
124 Write: SdClk is disabled, if no data is available. rkastl 4928d 13h /sdhc-sc-core/trunk/src/
123 Write: Must be able to halt SdClk, rest is done. rkastl 4928d 13h /sdhc-sc-core/trunk/src/
122 SdController: Initial read support rkastl 4928d 17h /sdhc-sc-core/trunk/src/

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