URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] - Rev 160

Rev	Log message	Author	Age	Path
137	Regression test suite: Removed unneeded testbenches from the makefile. Only complete reusable blocks are tested from now on.	rkastl	4923d 22h	/sdhc-sc-core/trunk/src/
136	SDHC: - SdData refactored to use a single counter - TestWbMaster added to TbdSd (not functional yet)	rkastl	4923d 22h	/sdhc-sc-core/trunk/src/
135	Multiple-Inclusion-Protection to SystemVerilog files added Stops using relative paths in `includes. instead +incdir has to be used.	rkastl	4923d 22h	/sdhc-sc-core/trunk/src/
134	SdData: Further refactoring.	rkastl	4923d 22h	/sdhc-sc-core/trunk/src/
133	SdData: Further refactoring	rkastl	4923d 22h	/sdhc-sc-core/trunk/src/
132	SdData: Refactoring, not done. Testbench works again, but does not really test anything.	rkastl	4923d 22h	/sdhc-sc-core/trunk/src/
130	SdClockMaster: Formal verification	rkastl	4923d 22h	/sdhc-sc-core/trunk/src/
129	SdClockMaster: Redesigned, not finished. Tb with PSL assertions.	rkastl	4923d 22h	/sdhc-sc-core/trunk/src/
128	Sim: Support for psl files added.	rkastl	4923d 22h	/sdhc-sc-core/trunk/src/
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4923d 22h	/sdhc-sc-core/trunk/src/