URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] - Rev 174

Rev	Log message	Author	Age	Path
149	SdBFM: + mailbox mode	rkastl	4912d 12h	/sdhc-sc-core/trunk/src/
148	SdVerification: + CardModel: Execution thread which starts initialization and then receives token and parses them. TbdSd: + Added SdWbSdSynchronization.	rkastl	4912d 12h	/sdhc-sc-core/trunk/src/
147	Sd-Core: + Added checking of Busy signal after write	rkastl	4912d 12h	/sdhc-sc-core/trunk/src/
146	SdClockMaster: + fixed output of data at negedge of sclk in high speed mode	rkastl	4912d 12h	/sdhc-sc-core/trunk/src/
145	Verification: + SdCardModel and SdBFM seperated	rkastl	4912d 12h	/sdhc-sc-core/trunk/src/
144	Simulation files for tbTbdSd created. tbTbdSd is not done and TestWbMaster seems to be lost.	rkastl	4912d 12h	/sdhc-sc-core/trunk/src/
140	Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete verification tb anyway.	rkastl	4912d 12h	/sdhc-sc-core/trunk/src/
139	Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in the complete verification environment anyway.	rkastl	4912d 12h	/sdhc-sc-core/trunk/src/
138	Removed testbench for unitSdCmd because it was a weak testbench and the functionality is tested in the SdVerificationTestbench anyway.	rkastl	4912d 12h	/sdhc-sc-core/trunk/src/
137	Regression test suite: Removed unneeded testbenches from the makefile. Only complete reusable blocks are tested from now on.	rkastl	4912d 12h	/sdhc-sc-core/trunk/src/