URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] - Rev 185

Rev	Log message	Author	Age	Path
159	Verification: Further work: Checking RAM Actions and reading data is still missing	rkastl	4892d 20h	/sdhc-sc-core/trunk/src/
158	Verification: Work on Checking Functional coverage	rkastl	4892d 20h	/sdhc-sc-core/trunk/src/
157	Verification: Testcase with Reads works but Verification not completly implemented.	rkastl	4892d 20h	/sdhc-sc-core/trunk/src/
156	SdVerification: + Split a SdCoreTransaction into multiple WbTransactions: Proof of Concept with a ReadSingleBlock-Transaction + Finish after certain amount of time and present simulation result	rkastl	4892d 20h	/sdhc-sc-core/trunk/src/
155	SdVerification: continue to work on it, not done.	rkastl	4892d 20h	/sdhc-sc-core/trunk/src/
154	SdVerification: - started sending with mailboxes	rkastl	4892d 20h	/sdhc-sc-core/trunk/src/
153	SdVerification: further development, not done by far	rkastl	4892d 20h	/sdhc-sc-core/trunk/src/
152	SdClockMaster: Generate InStrobe so that it the sd bus gets captured on the rising edge of the clock in high speed mode	rkastl	4892d 20h	/sdhc-sc-core/trunk/src/
151	Verification: + redesign: not functional yet	rkastl	4892d 20h	/sdhc-sc-core/trunk/src/
150	Testbed: + Simulation made possible + Write works - Sometimes the alignment in the block is not right	rkastl	4892d 20h	/sdhc-sc-core/trunk/src/