URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] - Rev 170

Rev	Log message	Author	Age	Path
148	SdVerification: + CardModel: Execution thread which starts initialization and then receives token and parses them. TbdSd: + Added SdWbSdSynchronization.	rkastl	4921d 01h	/sdhc-sc-core/trunk/src/grpSd/
147	Sd-Core: + Added checking of Busy signal after write	rkastl	4921d 01h	/sdhc-sc-core/trunk/src/grpSd/
146	SdClockMaster: + fixed output of data at negedge of sclk in high speed mode	rkastl	4921d 01h	/sdhc-sc-core/trunk/src/grpSd/
145	Verification: + SdCardModel and SdBFM seperated	rkastl	4921d 01h	/sdhc-sc-core/trunk/src/grpSd/
144	Simulation files for tbTbdSd created. tbTbdSd is not done and TestWbMaster seems to be lost.	rkastl	4921d 01h	/sdhc-sc-core/trunk/src/grpSd/
140	Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete verification tb anyway.	rkastl	4921d 01h	/sdhc-sc-core/trunk/src/grpSd/
139	Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in the complete verification environment anyway.	rkastl	4921d 01h	/sdhc-sc-core/trunk/src/grpSd/
138	Removed testbench for unitSdCmd because it was a weak testbench and the functionality is tested in the SdVerificationTestbench anyway.	rkastl	4921d 01h	/sdhc-sc-core/trunk/src/grpSd/
136	SDHC: - SdData refactored to use a single counter - TestWbMaster added to TbdSd (not functional yet)	rkastl	4921d 01h	/sdhc-sc-core/trunk/src/grpSd/
135	Multiple-Inclusion-Protection to SystemVerilog files added Stops using relative paths in `includes. instead +incdir has to be used.	rkastl	4921d 01h	/sdhc-sc-core/trunk/src/grpSd/