URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdVerificationTestbench/] - Rev 177

Rev	Log message	Author	Age	Path
124	Write: SdClk is disabled, if no data is available.	rkastl	4936d 07h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4936d 07h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
122	SdController: Initial read support	rkastl	4936d 10h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
121	SdWbSlave inserted into SdTop. SdController does not use it yet.	rkastl	4936d 10h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
113	Read with single block works on cards, but not in simulation. SdData.sv sends data with one "XXXX" cycle right before the crc.	rkastl	4936d 11h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
111	Sclk moved to neg. edge -> setup and hold times for fast mode are easier to reach. (only micro sd does not work in fast mode).	rkastl	4936d 11h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
110	All except microsd work in highspeed mode.	rkastl	4936d 11h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
109	Added a data ram.	rkastl	4936d 11h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
108	Added a ram to the testbed	rkastl	4936d 11h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
106	Fixes #29: All cards respond, but they do not all work.	rkastl	4936d 11h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/