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[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdVerificationTestbench/] - Rev 185

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Rev	Log message	Author	Age	Path
136	SDHC: - SdData refactored to use a single counter - TestWbMaster added to TbdSd (not functional yet)	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
135	Multiple-Inclusion-Protection to SystemVerilog files added Stops using relative paths in `includes. instead +incdir has to be used.	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
125	Write works in simulation	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
124	Write: SdClk is disabled, if no data is available.	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4924d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
122	SdController: Initial read support	rkastl	4924d 22h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
121	SdWbSlave inserted into SdTop. SdController does not use it yet.	rkastl	4924d 22h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
113	Read with single block works on cards, but not in simulation. SdData.sv sends data with one "XXXX" cycle right before the crc.	rkastl	4924d 22h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
111	Sclk moved to neg. edge -> setup and hold times for fast mode are easier to reach. (only micro sd does not work in fast mode).	rkastl	4924d 22h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/

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