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[/] [sdr_ctrl/] [trunk/] - Rev 57

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Rev Log message Author Age Path
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4519d 13h /sdr_ctrl/trunk/
36 Clean up dinesha 4520d 04h /sdr_ctrl/trunk/
35 Updated the New Documents - ver 0.1 dinesha 4520d 06h /sdr_ctrl/trunk/
34 Removed the older version dinesha 4520d 06h /sdr_ctrl/trunk/
33 clean up dinesha 4520d 06h /sdr_ctrl/trunk/
32 Debug is enable through +define dinesha 4522d 05h /sdr_ctrl/trunk/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4522d 05h /sdr_ctrl/trunk/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4522d 05h /sdr_ctrl/trunk/
29 SDRAM top and core related run file list are added into svn dinesha 4522d 05h /sdr_ctrl/trunk/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4522d 05h /sdr_ctrl/trunk/

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