URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 59

Rev	Log message	Author	Age	Path
39	Test Bench upgradation with bigger data burst size	dinesha	4511d 17h	/sdr_ctrl/trunk/
38	Port Name clean up	dinesha	4512d 22h	/sdr_ctrl/trunk/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4513d 00h	/sdr_ctrl/trunk/
36	Clean up	dinesha	4513d 15h	/sdr_ctrl/trunk/
35	Updated the New Documents - ver 0.1	dinesha	4513d 17h	/sdr_ctrl/trunk/
34	Removed the older version	dinesha	4513d 17h	/sdr_ctrl/trunk/
33	clean up	dinesha	4513d 17h	/sdr_ctrl/trunk/
32	Debug is enable through +define	dinesha	4515d 16h	/sdr_ctrl/trunk/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4515d 16h	/sdr_ctrl/trunk/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4515d 16h	/sdr_ctrl/trunk/