URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 72

Rev	Log message	Author	Age	Path
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4561d 05h	/sdr_ctrl/trunk/verif/
26	invalid log files are removed	dinesha	4561d 05h	/sdr_ctrl/trunk/verif/
25	tb.sv is renamed as tb_top	dinesha	4561d 05h	/sdr_ctrl/trunk/verif/
24	Clean Up	dinesha	4561d 05h	/sdr_ctrl/trunk/verif/
22	Pad sdram clock added	dinesha	4562d 10h	/sdr_ctrl/trunk/verif/
21	Clean up	dinesha	4562d 10h	/sdr_ctrl/trunk/verif/
20	8 Bit SDARM support is added	dinesha	4564d 05h	/sdr_ctrl/trunk/verif/
19	8 Bit SDRAM Support added	dinesha	4564d 05h	/sdr_ctrl/trunk/verif/
18	8 Bit SDRAM Support is added	dinesha	4564d 05h	/sdr_ctrl/trunk/verif/
17	micron 8 bit memory models are added into svn	dinesha	4564d 05h	/sdr_ctrl/trunk/verif/