URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 133

Rev	Log message	Author	Age	Path
110	split out more ip-xact components added sw sources	jt_eaton	4485d 21h	/socgen/trunk/tools/
107	added designCfg files to all modules	jt_eaton	4490d 06h	/socgen/trunk/tools/
106	checked in orp_soc project step 2	jt_eaton	4495d 23h	/socgen/trunk/tools/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4500d 20h	/socgen/trunk/tools/
103	added user guide resynced to local repository	jt_eaton	4520d 20h	/socgen/trunk/tools/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4583d 17h	/socgen/trunk/tools/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4596d 01h	/socgen/trunk/tools/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4638d 18h	/socgen/trunk/tools/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4674d 23h	/socgen/trunk/tools/
96	hierConnections now create ports	jt_eaton	4748d 19h	/socgen/trunk/tools/