URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 114

Rev	Log message	Author	Age	Path
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5003d 08h	/socgen/trunk/tools/bin/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5011d 10h	/socgen/trunk/tools/bin/
67	updated installs	jt_eaton	5021d 02h	/socgen/trunk/tools/bin/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5022d 02h	/socgen/trunk/tools/bin/
65	added params.sim to sims updated install's	jt_eaton	5027d 02h	/socgen/trunk/tools/bin/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5035d 01h	/socgen/trunk/tools/bin/
59	added filelist.core to syn dirs to customize core	jt_eaton	5035d 13h	/socgen/trunk/tools/bin/
57	Now generate all filelists from xml files	jt_eaton	5036d 04h	/socgen/trunk/tools/bin/
56	soc_builder now builds verilog from xml files	jt_eaton	5041d 13h	/socgen/trunk/tools/bin/
54	now set up fpga targets from xml files	jt_eaton	5044d 10h	/socgen/trunk/tools/bin/