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[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 133

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Rev Log message Author Age Path
88 added xml files for test benches
added gEDA sym sch starter templates
jt_eaton 4838d 06h /socgen/trunk/tools/bin/
86 split out all fpgas into families
added fpga pad_ring level
jt_eaton 4856d 20h /socgen/trunk/tools/bin/
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines
jt_eaton 4863d 19h /socgen/trunk/tools/bin/
84 removed unneeded files jt_eaton 4914d 01h /socgen/trunk/tools/bin/
83 added design.soc files
xml files now 99% 1685 complient
jt_eaton 4914d 05h /socgen/trunk/tools/bin/
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact
jt_eaton 4928d 23h /socgen/trunk/tools/bin/
81 morphing xml files to use 1685
removed log directories
jt_eaton 4950d 05h /socgen/trunk/tools/bin/
80 now generate all sims and syns param and filelists for xml jt_eaton 4979d 20h /socgen/trunk/tools/bin/
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory
jt_eaton 4988d 07h /socgen/trunk/tools/bin/
75 added linting using verilator jt_eaton 4991d 23h /socgen/trunk/tools/bin/

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