URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [sw/] - Rev 312

Rev	Log message	Author	Age	Path
87	abort gracfullt if memory bank switching does not work	arniml	7406d 14h	/t48/tags/rel_0_3_beta/sw/
85	initial check-in	arniml	7406d 19h	/t48/tags/rel_0_3_beta/sw/
74	enhance pass/fail detection	arniml	7413d 19h	/t48/tags/rel_0_3_beta/sw/
70	clean test cell before make	arniml	7419d 12h	/t48/tags/rel_0_3_beta/sw/
69	fix name of istrobe	arniml	7419d 12h	/t48/tags/rel_0_3_beta/sw/
61	expand script for dump compare	arniml	7421d 09h	/t48/tags/rel_0_3_beta/sw/
58	add periodic interrupt	arniml	7422d 09h	/t48/tags/rel_0_3_beta/sw/
57	abort if no interrupt occurs	arniml	7422d 09h	/t48/tags/rel_0_3_beta/sw/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7423d 10h	/t48/tags/rel_0_3_beta/sw/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7423d 10h	/t48/tags/rel_0_3_beta/sw/