OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [sw/] - Rev 329

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
87 abort gracfullt if memory bank switching does not work arniml 7373d 00h /t48/tags/rel_0_3_beta/sw/
85 initial check-in arniml 7373d 05h /t48/tags/rel_0_3_beta/sw/
74 enhance pass/fail detection arniml 7380d 06h /t48/tags/rel_0_3_beta/sw/
70 clean test cell before make arniml 7385d 22h /t48/tags/rel_0_3_beta/sw/
69 fix name of istrobe arniml 7385d 22h /t48/tags/rel_0_3_beta/sw/
61 expand script for dump compare arniml 7387d 19h /t48/tags/rel_0_3_beta/sw/
58 add periodic interrupt arniml 7388d 19h /t48/tags/rel_0_3_beta/sw/
57 abort if no interrupt occurs arniml 7388d 19h /t48/tags/rel_0_3_beta/sw/
52 + fix bug in PSW[3]
+ read SP properly for dump
arniml 7389d 20h /t48/tags/rel_0_3_beta/sw/
51 + implement Port1 and Port2
+ connect T0 and T1
+ return proper program memory contents
arniml 7389d 20h /t48/tags/rel_0_3_beta/sw/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.