URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_4_beta/] - Rev 331

Rev	Log message	Author	Age	Path
119	add int_in_progress_o to entity of int module	arniml	7285d 06h	/t48/tags/rel_0_4_beta/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7285d 06h	/t48/tags/rel_0_4_beta/
117	add bug Program Memory bank can be switched during interrupt	arniml	7286d 07h	/t48/tags/rel_0_4_beta/
116	adapt to GHDL 0.12 / gcc 3.4.0	arniml	7314d 07h	/t48/tags/rel_0_4_beta/
115	extend description	arniml	7315d 11h	/t48/tags/rel_0_4_beta/
114	initial check-in	arniml	7319d 07h	/t48/tags/rel_0_4_beta/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7325d 16h	/t48/tags/rel_0_4_beta/
112	update tb_behav_c0 for new ROM layout	arniml	7325d 16h	/t48/tags/rel_0_4_beta/
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7325d 16h	/t48/tags/rel_0_4_beta/
110	exchange syn_rom for lpm_rom	arniml	7325d 16h	/t48/tags/rel_0_4_beta/