URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 342

Rev	Log message	Author	Age	Path
129	cleanup copyright notice	arniml	7292d 10h	/t48/tags/rel_0_5_beta/
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7299d 14h	/t48/tags/rel_0_5_beta/
127	+ log status of A11 properly during interrupt routines + trigger counter on negative edge of T1 instead of positive edge	arniml	7299d 15h	/t48/tags/rel_0_5_beta/
126	+ specify hex file for external ROM on i8039 command line + support for no_dump_compare file in test cell	arniml	7299d 15h	/t48/tags/rel_0_5_beta/
125	exclude from dump compare	arniml	7299d 15h	/t48/tags/rel_0_5_beta/
124	fix wrong handling of MB after return from interrupt	arniml	7300d 12h	/t48/tags/rel_0_5_beta/
123	support hex file for external ROM	arniml	7300d 12h	/t48/tags/rel_0_5_beta/
122	test MB after return from interrupt	arniml	7300d 12h	/t48/tags/rel_0_5_beta/
121	update bug description for Program Memory bank can be switched during interrupt	arniml	7303d 05h	/t48/tags/rel_0_5_beta/
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7303d 06h	/t48/tags/rel_0_5_beta/