URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 78

Rev	Log message	Author	Age	Path
58	add periodic interrupt	arniml	7398d 20h	/t48/tags/rel_0_5_beta/
57	abort if no interrupt occurs	arniml	7398d 20h	/t48/tags/rel_0_5_beta/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7399d 21h	/t48/tags/rel_0_5_beta/
55	add dependency to tb_behav_pack for decoder	arniml	7399d 22h	/t48/tags/rel_0_5_beta/
54	- add tb_istrobe_s	arniml	7399d 22h	/t48/tags/rel_0_5_beta/
53	make istrobe visible through testbench package	arniml	7399d 22h	/t48/tags/rel_0_5_beta/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7399d 22h	/t48/tags/rel_0_5_beta/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7399d 22h	/t48/tags/rel_0_5_beta/
49	Imported sources	arniml	7404d 23h	/t48/tags/rel_0_5_beta/
48	update copyright notice	arniml	7404d 23h	/t48/tags/rel_0_5_beta/