URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] [rtl/] - Rev 329

Rev	Log message	Author	Age	Path
86	update notice about expander port instructions	arniml	7363d 17h	/t48/tags/rel_0_5_beta/rtl/
78	adjust external timing of BUS	arniml	7369d 12h	/t48/tags/rel_0_5_beta/rtl/
77	move from std_logic_arith to numeric_std	arniml	7370d 05h	/t48/tags/rel_0_5_beta/rtl/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7370d 17h	/t48/tags/rel_0_5_beta/rtl/
72	removed superfluous signal from sensitivity list	arniml	7370d 17h	/t48/tags/rel_0_5_beta/rtl/
66	add temporary workaround for GHDL 0.11	arniml	7376d 10h	/t48/tags/rel_0_5_beta/rtl/
65	clean up sensitivity list	arniml	7376d 10h	/t48/tags/rel_0_5_beta/rtl/
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7376d 10h	/t48/tags/rel_0_5_beta/rtl/
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7376d 10h	/t48/tags/rel_0_5_beta/rtl/
62	initial check-in	arniml	7376d 10h	/t48/tags/rel_0_5_beta/rtl/