URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] - Rev 152

Rev	Log message	Author	Age	Path
132	stop simulation upon assertion error	arniml	7230d 21h	/t48/tags/rel_0_6_1_beta/
131	update	arniml	7230d 21h	/t48/tags/rel_0_6_1_beta/
130	initial check-in	arniml	7230d 21h	/t48/tags/rel_0_6_1_beta/
129	cleanup copyright notice	arniml	7293d 05h	/t48/tags/rel_0_6_1_beta/
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7300d 08h	/t48/tags/rel_0_6_1_beta/
127	+ log status of A11 properly during interrupt routines + trigger counter on negative edge of T1 instead of positive edge	arniml	7300d 09h	/t48/tags/rel_0_6_1_beta/
126	+ specify hex file for external ROM on i8039 command line + support for no_dump_compare file in test cell	arniml	7300d 09h	/t48/tags/rel_0_6_1_beta/
125	exclude from dump compare	arniml	7300d 09h	/t48/tags/rel_0_6_1_beta/
124	fix wrong handling of MB after return from interrupt	arniml	7301d 07h	/t48/tags/rel_0_6_1_beta/
123	support hex file for external ROM	arniml	7301d 07h	/t48/tags/rel_0_6_1_beta/