URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] - Rev 212

Rev	Log message	Author	Age	Path
192	update list for Wishbone toplevel	arniml	6836d 00h	/t48/tags/rel_0_6_1_beta/
191	preliminary version 0.2	arniml	6836d 03h	/t48/tags/rel_0_6_1_beta/
190	finalize change log for release 0.6 beta	arniml	6836d 21h	/t48/tags/rel_0_6_1_beta/
189	add bug report "Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"	arniml	6867d 23h	/t48/tags/rel_0_6_1_beta/
188	move check for int_pending_s into ea_i_='0' branch this fixes a glitch on PCH when an interrutp occurs during external program memory fetch	arniml	6868d 00h	/t48/tags/rel_0_6_1_beta/
187	Fix bug reports: "Target address of JMP to Program Memory Bank 1 corrupted by interrupt" "Return address of CALL to Program Memory Bank 1 corrupted by interrupt" int_in_progress_o was active one cycle before int_pending_o is asserted. this confused the mb multiplexer which determines the state of the memory bank selection flag	arniml	6868d 00h	/t48/tags/rel_0_6_1_beta/
186	update to version 0.2	arniml	6869d 01h	/t48/tags/rel_0_6_1_beta/
185	initial check-in	arniml	6873d 23h	/t48/tags/rel_0_6_1_beta/
184	initial check-in	arniml	6874d 00h	/t48/tags/rel_0_6_1_beta/
183	fix missing assignment to outclock	arniml	6874d 03h	/t48/tags/rel_0_6_1_beta/