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[/] [t48/] [tags/] [rel_0_6_1_beta/] [rtl/] - Rev 180

Rev	Log message	Author	Age	Path
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7167d 05h	/t48/tags/rel_0_6_1_beta/rtl/
149	update	arniml	7167d 05h	/t48/tags/rel_0_6_1_beta/rtl/
148	initial check-in	arniml	7167d 05h	/t48/tags/rel_0_6_1_beta/rtl/
145	remove PROG and end of XTAL2, see comment for details	arniml	7204d 07h	/t48/tags/rel_0_6_1_beta/rtl/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7204d 07h	/t48/tags/rel_0_6_1_beta/rtl/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7204d 08h	/t48/tags/rel_0_6_1_beta/rtl/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7204d 08h	/t48/tags/rel_0_6_1_beta/rtl/
138	Fix for: P1 constantly in push-pull mode in t8048	arniml	7205d 19h	/t48/tags/rel_0_6_1_beta/rtl/
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7248d 03h	/t48/tags/rel_0_6_1_beta/rtl/
129	cleanup copyright notice	arniml	7310d 11h	/t48/tags/rel_0_6_1_beta/rtl/