URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] [rtl/] - Rev 203

Rev	Log message	Author	Age	Path
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7062d 19h	/t48/tags/rel_0_6_1_beta/rtl/
157	removed obsolete constant	arniml	7183d 15h	/t48/tags/rel_0_6_1_beta/rtl/
156	added hierarchy t8039_notri	arniml	7183d 15h	/t48/tags/rel_0_6_1_beta/rtl/
155	initial check-in	arniml	7183d 15h	/t48/tags/rel_0_6_1_beta/rtl/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7184d 12h	/t48/tags/rel_0_6_1_beta/rtl/
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7185d 11h	/t48/tags/rel_0_6_1_beta/rtl/
149	update	arniml	7185d 11h	/t48/tags/rel_0_6_1_beta/rtl/
148	initial check-in	arniml	7185d 11h	/t48/tags/rel_0_6_1_beta/rtl/
145	remove PROG and end of XTAL2, see comment for details	arniml	7222d 14h	/t48/tags/rel_0_6_1_beta/rtl/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7222d 14h	/t48/tags/rel_0_6_1_beta/rtl/