URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] [rtl/] - Rev 208

Rev	Log message	Author	Age	Path
167	simplify address range: - configuration range - Wishbone range	arniml	7039d 12h	/t48/tags/rel_0_6_1_beta/rtl/
166	assign default for state_s	arniml	7041d 04h	/t48/tags/rel_0_6_1_beta/rtl/
165	add component wb_master.vhd	arniml	7042d 03h	/t48/tags/rel_0_6_1_beta/rtl/
164	initial check-in	arniml	7042d 03h	/t48/tags/rel_0_6_1_beta/rtl/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7043d 03h	/t48/tags/rel_0_6_1_beta/rtl/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7074d 07h	/t48/tags/rel_0_6_1_beta/rtl/
157	removed obsolete constant	arniml	7195d 03h	/t48/tags/rel_0_6_1_beta/rtl/
156	added hierarchy t8039_notri	arniml	7195d 03h	/t48/tags/rel_0_6_1_beta/rtl/
155	initial check-in	arniml	7195d 03h	/t48/tags/rel_0_6_1_beta/rtl/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7196d 01h	/t48/tags/rel_0_6_1_beta/rtl/