URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] [rtl/] - Rev 329

Rev	Log message	Author	Age	Path
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	6957d 20h	/t48/tags/rel_0_6_1_beta/rtl/
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	6959d 08h	/t48/tags/rel_0_6_1_beta/rtl/
177	Implement db_dir_o glitch-safe	arniml	6959d 08h	/t48/tags/rel_0_6_1_beta/rtl/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	6959d 08h	/t48/tags/rel_0_6_1_beta/rtl/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	6960d 11h	/t48/tags/rel_0_6_1_beta/rtl/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	6989d 08h	/t48/tags/rel_0_6_1_beta/rtl/
171	remove obsolete output stack_high_o	arniml	6990d 08h	/t48/tags/rel_0_6_1_beta/rtl/
169	initial check-in	arniml	6991d 20h	/t48/tags/rel_0_6_1_beta/rtl/
168	change address range of wb_master	arniml	6991d 20h	/t48/tags/rel_0_6_1_beta/rtl/
167	simplify address range: - configuration range - Wishbone range	arniml	6991d 20h	/t48/tags/rel_0_6_1_beta/rtl/