URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 157

Rev	Log message	Author	Age	Path
137	add link to COMPILE_LIST	arniml	7262d 01h	/t48/tags/rel_0_6_beta/
136	initial check-in	arniml	7262d 01h	/t48/tags/rel_0_6_beta/
135	add bug PSENn Timing	arniml	7266d 11h	/t48/tags/rel_0_6_beta/
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7266d 21h	/t48/tags/rel_0_6_beta/
133	add checks for PSEN	arniml	7266d 21h	/t48/tags/rel_0_6_beta/
132	stop simulation upon assertion error	arniml	7266d 21h	/t48/tags/rel_0_6_beta/
131	update	arniml	7266d 21h	/t48/tags/rel_0_6_beta/
130	initial check-in	arniml	7266d 21h	/t48/tags/rel_0_6_beta/
129	cleanup copyright notice	arniml	7329d 04h	/t48/tags/rel_0_6_beta/
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7336d 08h	/t48/tags/rel_0_6_beta/