URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 312

Rev	Log message	Author	Age	Path
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	6974d 18h	/t48/tags/rel_0_6_beta/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	6974d 18h	/t48/tags/rel_0_6_beta/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	6974d 18h	/t48/tags/rel_0_6_beta/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7003d 15h	/t48/tags/rel_0_6_beta/
171	remove obsolete output stack_high_o	arniml	7004d 15h	/t48/tags/rel_0_6_beta/
170	intermediate update	arniml	7005d 21h	/t48/tags/rel_0_6_beta/
169	initial check-in	arniml	7006d 03h	/t48/tags/rel_0_6_beta/
168	change address range of wb_master	arniml	7006d 03h	/t48/tags/rel_0_6_beta/
167	simplify address range: - configuration range - Wishbone range	arniml	7006d 03h	/t48/tags/rel_0_6_beta/
166	assign default for state_s	arniml	7007d 18h	/t48/tags/rel_0_6_beta/