URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 83

Rev	Log message	Author	Age	Path
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7410d 04h	/t48/tags/rel_0_6_beta/
62	initial check-in	arniml	7410d 04h	/t48/tags/rel_0_6_beta/
61	expand script for dump compare	arniml	7412d 01h	/t48/tags/rel_0_6_beta/
60	+ add marker for injected calls + suppress intstruction strobes for injected calls	arniml	7413d 01h	/t48/tags/rel_0_6_beta/
59	increment prescaler with MSTATE4	arniml	7413d 01h	/t48/tags/rel_0_6_beta/
58	add periodic interrupt	arniml	7413d 01h	/t48/tags/rel_0_6_beta/
57	abort if no interrupt occurs	arniml	7413d 01h	/t48/tags/rel_0_6_beta/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7414d 02h	/t48/tags/rel_0_6_beta/
55	add dependency to tb_behav_pack for decoder	arniml	7414d 02h	/t48/tags/rel_0_6_beta/
54	- add tb_istrobe_s	arniml	7414d 02h	/t48/tags/rel_0_6_beta/