URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] - Rev 167

Rev	Log message	Author	Age	Path
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7380d 16h	/t48/tags/rel_0_6_beta/rtl/
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7384d 08h	/t48/tags/rel_0_6_beta/rtl/
119	add int_in_progress_o to entity of int module	arniml	7384d 08h	/t48/tags/rel_0_6_beta/rtl/
108	Fix for: External Program Memory ignored when EA = 0	arniml	7425d 08h	/t48/tags/rel_0_6_beta/rtl/
107	tie EA to '1'	arniml	7425d 08h	/t48/tags/rel_0_6_beta/rtl/
106	clean-up use of ea_i	arniml	7425d 08h	/t48/tags/rel_0_6_beta/rtl/
101	assert p2_read_p2_o when expander port is read	arniml	7428d 15h	/t48/tags/rel_0_6_beta/rtl/
100	reorder data_o generation	arniml	7428d 15h	/t48/tags/rel_0_6_beta/rtl/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7428d 16h	/t48/tags/rel_0_6_beta/rtl/
92	work around bug in Quartus II 4.0	arniml	7429d 14h	/t48/tags/rel_0_6_beta/rtl/