URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 123

Rev	Log message	Author	Age	Path
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7363d 01h	/t48/tags/rel_1_0/
102	update for changes in address space of external memory	arniml	7363d 01h	/t48/tags/rel_1_0/
101	assert p2_read_p2_o when expander port is read	arniml	7363d 01h	/t48/tags/rel_1_0/
100	reorder data_o generation	arniml	7363d 01h	/t48/tags/rel_1_0/
99	initial check-in	arniml	7363d 01h	/t48/tags/rel_1_0/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7363d 02h	/t48/tags/rel_1_0/
97	initial check-in	arniml	7363d 02h	/t48/tags/rel_1_0/
96	select dedicated directorie(s) for regression	arniml	7364d 00h	/t48/tags/rel_1_0/
95	check counter inactivity	arniml	7364d 00h	/t48/tags/rel_1_0/
94	initial check-in	arniml	7364d 00h	/t48/tags/rel_1_0/