URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 198

Rev	Log message	Author	Age	Path
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	6973d 20h	/t48/tags/rel_1_0/
177	Implement db_dir_o glitch-safe	arniml	6973d 20h	/t48/tags/rel_1_0/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	6973d 20h	/t48/tags/rel_1_0/
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	6974d 23h	/t48/tags/rel_1_0/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	6974d 23h	/t48/tags/rel_1_0/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	6974d 23h	/t48/tags/rel_1_0/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7003d 20h	/t48/tags/rel_1_0/
171	remove obsolete output stack_high_o	arniml	7004d 20h	/t48/tags/rel_1_0/
170	intermediate update	arniml	7006d 02h	/t48/tags/rel_1_0/
169	initial check-in	arniml	7006d 07h	/t48/tags/rel_1_0/