URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 97

Rev	Log message	Author	Age	Path
77	move from std_logic_arith to numeric_std	arniml	7449d 07h	/t48/tags/rel_1_0/
76	initial check-in	arniml	7449d 11h	/t48/tags/rel_1_0/
75	remove obsolete design unit	arniml	7449d 11h	/t48/tags/rel_1_0/
74	enhance pass/fail detection	arniml	7449d 19h	/t48/tags/rel_1_0/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7449d 20h	/t48/tags/rel_1_0/
72	removed superfluous signal from sensitivity list	arniml	7449d 20h	/t48/tags/rel_1_0/
71	add T8039 and its testbench	arniml	7455d 12h	/t48/tags/rel_1_0/
70	clean test cell before make	arniml	7455d 12h	/t48/tags/rel_1_0/
69	fix name of istrobe	arniml	7455d 12h	/t48/tags/rel_1_0/
68	connect T0 and T1 to P1	arniml	7455d 12h	/t48/tags/rel_1_0/