URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] - Rev 187

Rev	Log message	Author	Age	Path
155	initial check-in	arniml	7159d 02h	/t48/tags/rel_1_0/rtl/vhdl/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7160d 00h	/t48/tags/rel_1_0/rtl/vhdl/
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7160d 23h	/t48/tags/rel_1_0/rtl/vhdl/
149	update	arniml	7160d 23h	/t48/tags/rel_1_0/rtl/vhdl/
148	initial check-in	arniml	7160d 23h	/t48/tags/rel_1_0/rtl/vhdl/
145	remove PROG and end of XTAL2, see comment for details	arniml	7198d 02h	/t48/tags/rel_1_0/rtl/vhdl/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7198d 02h	/t48/tags/rel_1_0/rtl/vhdl/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7198d 02h	/t48/tags/rel_1_0/rtl/vhdl/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7198d 02h	/t48/tags/rel_1_0/rtl/vhdl/
138	Fix for: P1 constantly in push-pull mode in t8048	arniml	7199d 13h	/t48/tags/rel_1_0/rtl/vhdl/