URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] - Rev 207

Rev	Log message	Author	Age	Path
166	assign default for state_s	arniml	7030d 16h	/t48/tags/rel_1_0/rtl/vhdl/
165	add component wb_master.vhd	arniml	7031d 15h	/t48/tags/rel_1_0/rtl/vhdl/
164	initial check-in	arniml	7031d 15h	/t48/tags/rel_1_0/rtl/vhdl/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7032d 15h	/t48/tags/rel_1_0/rtl/vhdl/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7063d 19h	/t48/tags/rel_1_0/rtl/vhdl/
157	removed obsolete constant	arniml	7184d 15h	/t48/tags/rel_1_0/rtl/vhdl/
156	added hierarchy t8039_notri	arniml	7184d 16h	/t48/tags/rel_1_0/rtl/vhdl/
155	initial check-in	arniml	7184d 16h	/t48/tags/rel_1_0/rtl/vhdl/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7185d 13h	/t48/tags/rel_1_0/rtl/vhdl/
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7186d 12h	/t48/tags/rel_1_0/rtl/vhdl/