URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [sw/] - Rev 326

Rev	Log message	Author	Age	Path
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	7041d 10h	/t48/tags/rel_1_0/sw/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7267d 10h	/t48/tags/rel_1_0/sw/
132	stop simulation upon assertion error	arniml	7311d 05h	/t48/tags/rel_1_0/sw/
131	update	arniml	7311d 05h	/t48/tags/rel_1_0/sw/
130	initial check-in	arniml	7311d 05h	/t48/tags/rel_1_0/sw/
127	+ log status of A11 properly during interrupt routines + trigger counter on negative edge of T1 instead of positive edge	arniml	7380d 17h	/t48/tags/rel_1_0/sw/
126	+ specify hex file for external ROM on i8039 command line + support for no_dump_compare file in test cell	arniml	7380d 17h	/t48/tags/rel_1_0/sw/
125	exclude from dump compare	arniml	7380d 17h	/t48/tags/rel_1_0/sw/
124	fix wrong handling of MB after return from interrupt	arniml	7381d 15h	/t48/tags/rel_1_0/sw/
123	support hex file for external ROM	arniml	7381d 15h	/t48/tags/rel_1_0/sw/