URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] - Rev 166

Rev	Log message	Author	Age	Path
146	add bug RD' and WR' not asserted for INS A, BUS and OUTL BUS, A	arniml	7201d 09h	/t48/tags/rel_1_1/
145	remove PROG and end of XTAL2, see comment for details	arniml	7201d 10h	/t48/tags/rel_1_1/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7201d 10h	/t48/tags/rel_1_1/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7201d 11h	/t48/tags/rel_1_1/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7201d 11h	/t48/tags/rel_1_1/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7201d 11h	/t48/tags/rel_1_1/
140	remove tAW sanity check conflicts with OUTL A, BUS	arniml	7201d 11h	/t48/tags/rel_1_1/
139	add bug P1 constantly in push-pull mode in t8048	arniml	7202d 21h	/t48/tags/rel_1_1/
138	Fix for: P1 constantly in push-pull mode in t8048	arniml	7202d 21h	/t48/tags/rel_1_1/
137	add link to COMPILE_LIST	arniml	7240d 10h	/t48/tags/rel_1_1/