URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] - Rev 170

Rev	Log message	Author	Age	Path
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7164d 09h	/t48/tags/rel_1_1/
149	update	arniml	7164d 09h	/t48/tags/rel_1_1/
148	initial check-in	arniml	7164d 09h	/t48/tags/rel_1_1/
147	initial check-in for release 0.5 BETA	arniml	7200d 11h	/t48/tags/rel_1_1/
146	add bug RD' and WR' not asserted for INS A, BUS and OUTL BUS, A	arniml	7201d 11h	/t48/tags/rel_1_1/
145	remove PROG and end of XTAL2, see comment for details	arniml	7201d 12h	/t48/tags/rel_1_1/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7201d 12h	/t48/tags/rel_1_1/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7201d 13h	/t48/tags/rel_1_1/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7201d 13h	/t48/tags/rel_1_1/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7201d 13h	/t48/tags/rel_1_1/