URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] [sw/] - Rev 312

Rev	Log message	Author	Age	Path
184	initial check-in	arniml	6883d 18h	/t48/tags/rel_1_1/sw/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	6974d 19h	/t48/tags/rel_1_1/sw/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7200d 19h	/t48/tags/rel_1_1/sw/
132	stop simulation upon assertion error	arniml	7244d 14h	/t48/tags/rel_1_1/sw/
131	update	arniml	7244d 14h	/t48/tags/rel_1_1/sw/
130	initial check-in	arniml	7244d 14h	/t48/tags/rel_1_1/sw/
127	+ log status of A11 properly during interrupt routines + trigger counter on negative edge of T1 instead of positive edge	arniml	7314d 02h	/t48/tags/rel_1_1/sw/
126	+ specify hex file for external ROM on i8039 command line + support for no_dump_compare file in test cell	arniml	7314d 02h	/t48/tags/rel_1_1/sw/
125	exclude from dump compare	arniml	7314d 02h	/t48/tags/rel_1_1/sw/
124	fix wrong handling of MB after return from interrupt	arniml	7315d 00h	/t48/tags/rel_1_1/sw/