URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] - Rev 100

Rev	Log message	Author	Age	Path
80	Grouping some instructions that have the same behavioral.	gabrieloshiro	5622d 13h	/t6507lp/trunk/rtl/
79	ALU testbench added.	gabrieloshiro	5622d 14h	/t6507lp/trunk/rtl/
78	ZPG coded and simulated.	creep	5622d 14h	/t6507lp/trunk/rtl/
77	ZPG coded. Simulation is halfway.	creep	5622d 15h	/t6507lp/trunk/rtl/
76	ABS write instructions were not simulated. Also added some initial ZPG simulation.	creep	5622d 15h	/t6507lp/trunk/rtl/
75	First working version!	gabrieloshiro	5622d 15h	/t6507lp/trunk/rtl/
71	Four addressing modes are simulated: immediate, accumulator, implied and absolute. The simulation was done using a testbench that contains a small memory inside.	creep	5622d 16h	/t6507lp/trunk/rtl/
70	Fixed several timing. Registered outputs working. Only three adressing modes coded, the previous coding was erased.	creep	5626d 12h	/t6507lp/trunk/rtl/
68	The FSM module is now parametrized. Also, several changes were made to remove most of the lint warnings.	creep	5626d 14h	/t6507lp/trunk/rtl/
67	File name change to lowercase. HAL says so!	creep	5626d 16h	/t6507lp/trunk/rtl/