URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] - Rev 147

Rev	Log message	Author	Age	Path
113	Timescale was unified.	gabrieloshiro	5607d 06h	/t6507lp/trunk/rtl/
112	Created a global timescale file for the project.	creep	5607d 06h	/t6507lp/trunk/rtl/
111	Performed some linting after coding was finished.	creep	5607d 22h	/t6507lp/trunk/rtl/
110	All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage.	creep	5607d 23h	/t6507lp/trunk/rtl/
109	PLA and PLP are coded and simulated.	creep	5608d 02h	/t6507lp/trunk/rtl/
108	PHA and PHP are coded and simulated.	creep	5608d 02h	/t6507lp/trunk/rtl/
107	The RTS instruction is working fine. Coded and simulated.	creep	5608d 03h	/t6507lp/trunk/rtl/
106	First stable version. Things seems to be working. Simulation is currently at 20%.	gabrieloshiro	5608d 03h	/t6507lp/trunk/rtl/
105	The RTI instruction is working fine. Coded and simulated.	creep	5608d 04h	/t6507lp/trunk/rtl/
104	The BRK instruction is working. The reset vector was tested also.	creep	5608d 06h	/t6507lp/trunk/rtl/