URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] - Rev 165

Rev	Log message	Author	Age	Path
141	t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name.	creep	5624d 10h	/t6507lp/trunk/rtl/
140	Variable names were changed according to coding guidelines.	gabrieloshiro	5624d 10h	/t6507lp/trunk/rtl/
139	t6507lp_package.v was renamed to avoid uppercase.	creep	5624d 10h	/t6507lp/trunk/rtl/
136	Some minor coding style changes.	gabrieloshiro	5625d 06h	/t6507lp/trunk/rtl/
129	RTL and e files are truly linked now. Some very early coverage is done.	creep	5629d 06h	/t6507lp/trunk/rtl/
128	$write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized.	gabrieloshiro	5629d 09h	/t6507lp/trunk/rtl/
127	Testbench created. Simulation is almost done! Everything seems to be working fine.	gabrieloshiro	5629d 10h	/t6507lp/trunk/rtl/
126	Added a wrapper for the ALU. This file creates the clock for Specman.	creep	5629d 11h	/t6507lp/trunk/rtl/
120	Added some extra commentaries.	creep	5631d 06h	/t6507lp/trunk/rtl/
119	removing old file.	creep	5631d 09h	/t6507lp/trunk/rtl/