URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 158

Rev	Log message	Author	Age	Path
128	$write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized.	gabrieloshiro	5574d 04h	/t6507lp/trunk/rtl/verilog/
127	Testbench created. Simulation is almost done! Everything seems to be working fine.	gabrieloshiro	5574d 05h	/t6507lp/trunk/rtl/verilog/
126	Added a wrapper for the ALU. This file creates the clock for Specman.	creep	5574d 06h	/t6507lp/trunk/rtl/verilog/
120	Added some extra commentaries.	creep	5576d 01h	/t6507lp/trunk/rtl/verilog/
119	removing old file.	creep	5576d 04h	/t6507lp/trunk/rtl/verilog/
118	The top level name was in uppercase. The correct is lowercase.	creep	5576d 05h	/t6507lp/trunk/rtl/verilog/
117	Fixed the top level and connected the entire project.	creep	5576d 05h	/t6507lp/trunk/rtl/verilog/
116	Changed the module instantiation into the dot form.	creep	5576d 06h	/t6507lp/trunk/rtl/verilog/
115	Renamed the signal control. It is mem_rw now.	creep	5576d 06h	/t6507lp/trunk/rtl/verilog/
114	Created a global timescale file for the project. Added to the top module.	creep	5576d 06h	/t6507lp/trunk/rtl/verilog/