URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 56

Rev	Log message	Author	Age	Path
28	More documentation.	gabrieloshiro	5608d 02h	/t6507lp/trunk/rtl/verilog/
27	Added the pipelining support for a few addressing modes. Still working on absolute addressing mode.	creep	5608d 02h	/t6507lp/trunk/rtl/verilog/
26	I`m still finishing the documentation. But the file should work by now.	gabrieloshiro	5610d 19h	/t6507lp/trunk/rtl/verilog/
25	Package file contains all important constants and local parameters. It assigns constant values for opcodes aliases, processor status register indexes, and addressing modes. It is going to help people to understand the code. T65 project has a lot of constants inside its codes. So it is hard to understand it.	gabrieloshiro	5610d 21h	/t6507lp/trunk/rtl/verilog/
24	Added some simple logic to a few states. Connection with the ALU is pending.	creep	5610d 21h	/t6507lp/trunk/rtl/verilog/
23	Updated file header standard.	creep	5610d 22h	/t6507lp/trunk/rtl/verilog/
22	Signal and module name convention.	creep	5610d 22h	/t6507lp/trunk/rtl/verilog/
21	* empty log message *	creep	5610d 23h	/t6507lp/trunk/rtl/verilog/
20	Added immediate, absolute and zero page addressing modes FSM branches. Five other modes still needed. Internal signal handling and temp registers still missing.	creep	5610d 23h	/t6507lp/trunk/rtl/verilog/
19	Parameters removed.	creep	5611d 00h	/t6507lp/trunk/rtl/verilog/