URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 88

Rev	Log message	Author	Age	Path
64	Constant were wrong.	gabrieloshiro	5635d 14h	/t6507lp/trunk/rtl/verilog/
63	Fixed several HAL warnings. Still plenty to do.	creep	5635d 14h	/t6507lp/trunk/rtl/verilog/
62	The DUT file name changed.	creep	5635d 14h	/t6507lp/trunk/rtl/verilog/
61	File name change to lowercase. HAL says so!	creep	5635d 15h	/t6507lp/trunk/rtl/verilog/
60	File name change. HAL says so!	creep	5635d 15h	/t6507lp/trunk/rtl/verilog/
59	I`ve fixed some latch creation.	gabrieloshiro	5635d 15h	/t6507lp/trunk/rtl/verilog/
58	ALU with all opcodes ready for simulation.	gabrieloshiro	5635d 15h	/t6507lp/trunk/rtl/verilog/
57	A very simple testbench that checks the execution for a single instruction, i.e. no memory.	creep	5635d 16h	/t6507lp/trunk/rtl/verilog/
56	Several changes in the output logic to respect the pipelining.	creep	5635d 16h	/t6507lp/trunk/rtl/verilog/
55	ALU has all opcodes now! Comments inside ALU are completely wrong.	gabrieloshiro	5635d 17h	/t6507lp/trunk/rtl/verilog/