OpenCores

URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [testbench/] - Rev 41

Filtering Options

Rev	Log message	Author	Age	Path
17	Added fetch component for fetching from memory to instruction register Added additional testing for carryover to make sure it's correct	earlz	4406d 03h	/tinycpu/trunk/testbench/
16	Renamed incdec to carryover (see design for why). carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.	earlz	4409d 05h	/tinycpu/trunk/testbench/
15	Added README, LICENSE, and the (so far not created) incdec component	earlz	4411d 03h	/tinycpu/trunk/testbench/
14	Added ALU with all the operations we'll need. Synthesizes as well trivially	earlz	4411d 11h	/tinycpu/trunk/testbench/
12	registerfile has ports for every register now makefile now uses GHW file format for gtkwave instead of VCD	earlz	4411d 14h	/tinycpu/trunk/testbench/
11	Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge	earlz	4415d 04h	/tinycpu/trunk/testbench/
10	Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs	earlz	4415d 04h	/tinycpu/trunk/testbench/
9	Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench	earlz	4415d 12h	/tinycpu/trunk/testbench/
8	Added blockram for inferring actual block RAM. Now we need a memory controller, not a crappy memory emulation thing	earlz	4416d 11h	/tinycpu/trunk/testbench/
7	Changed memory to fix bound check error Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)	earlz	4416d 12h	/tinycpu/trunk/testbench/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.