URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] - Rev 95

Rev	Log message	Author	Age	Path
72	Added copyright header	ghutchis	6965d 23h	/tv80/trunk/
71	Ported UART from T80	ghutchis	7027d 03h	/tv80/trunk/
70	Added test for T16450 UART	ghutchis	7077d 22h	/tv80/trunk/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7077d 22h	/tv80/trunk/
68	Updated nwtest to reflect changes in register interface to simple_gmii. In particular, interrupt bits for packet arrival and sending now need to be explicitly cleared afterwards.	ghutchis	7085d 23h	/tv80/trunk/
67	Updated register generator based on testing with simple_gmii. Changed how interrupt output mux is created, fixed many bugs.	ghutchis	7085d 23h	/tv80/trunk/
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7085d 23h	/tv80/trunk/
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7085d 23h	/tv80/trunk/
64	Created rgen script and expanded available register types	ghutchis	7086d 21h	/tv80/trunk/
63	Added simple regression script. -r command runs all tests (serially), -c command checks results after all tests have completed.	ghutchis	7121d 02h	/tv80/trunk/